Ann Arbor, MI · Looking for hardware internships

Jaden Rhee

Electrical Engineering Student · Hardware & PCB Design

I design PCBs and the hardware around them, and write the firmware they run. Currently validating chassis-control ECUs at Bosch.

View projectsRésumé (PDF)

Projects

The View in 3D models come straight from the real KiCad and CAD files.

Isometric render of the JRWatch 4-layer smartwatch PCB
PCBLow-powerZephyrBLE

JRWatch, a Low-Power BLE Smartwatch

A 36 mm nRF52840 smartwatch board that sleeps at about 15 µA, designed entirely in code.

Problem
Most smartwatches last a few days on a charge because low power is an afterthought. I wanted a watch that runs for months on a 150 mAh cell, with every current number justified before ordering the board.
What I built
A 4-layer 36 x 36 mm board with an nRF52840, an nPM1300 PMIC with two switched power domains and a 370 nA ship mode, a BMI270 IMU for motion wake, and a Sharp memory-in-pixel display that holds a static watch face at about 4 µA. The schematic is written in SKiDL, placement and routing are scripted through the pcbnew API, and the Zephyr firmware builds in CI with a custom board definition. The OpenSCAD case is dimensioned from the board file.
Outcome
ERC and DRC are clean. The firmware fits in 231 KiB of flash and 40 KiB of RAM. The power budget works out to 4 to 8 months per charge, with each line cited in the verification report. Next step is confirming the numbers with a PPK2 at bring-up.

nRF52840 · Zephyr RTOS · SKiDL · KiCad · nPM1300 · BMI270 · C · OpenSCAD

GitHub
WiggleCam enclosure render, front view with four lenses and a grip
SystemsImagingPythonCAD

WiggleCam, a 4-Lens Wigglegram Camera

A handheld camera with four synchronized lenses that turns a shot into a looping 3D gif anyone can grab over a QR code.

Problem
Film wigglegram cameras need scanning and manual frame alignment, and multi-camera rigs ghost on moving subjects because the sensors fire at slightly different times. I also wanted sharing to work on any phone without an app.
What I built
Four 16 MP camera modules sit 40 mm apart behind the faceplate, clocked by an Arducam Camarray HAT that merges them into one stitched frame, so all four exposures happen at the same instant. Python code on a Raspberry Pi 5 splits the frame, aligns the views with phase correlation, applies a filter picked on the touchscreen, and renders a looping gif served over the camera's own Wi-Fi hotspot as a QR code. The body is parametric OpenSCAD with a BMS-protected 4x18650 supply.
Outcome
Design and firmware are done and the physical build is in progress. The bill of materials comes to about $550 with stock-checked parts and an estimated 4.4 hours of runtime.

Raspberry Pi 5 · Arducam Camarray · Python · OpenCV · PyQt · OpenSCAD

GitHub
Top render of the WiggleCam controller 4-layer PCB
PCBRP2040FirmwareVerification

WiggleCam Controller, an RP2040 Co-Processor Board

The RP2040 board that handles the camera's flash current control, shutter timing, and battery telemetry. Fully routed with zero DRC violations.

Problem
A Raspberry Pi 5 is not suited to hard real-time or analog work. The LED flash needs constant-current drive with hardware safety limits, the shutter needs reliable debounce, and the battery needs monitoring, none of which should steal cycles from image processing.
What I built
A 76 x 50 mm 4-layer board that sits between the Pi and the hardware over a 2x6 header mapped onto Pi 5 GPIO. The schematic is SKiDL, placement is scripted, low-speed nets go through Freerouting with a DRC gate at JLCPCB limits at every stage, and a verification pass measures the finished layout against published design guidance. The Pico SDK firmware exposes an I2C register file with a UART fallback.
Outcome
Fully routed with zero DRC violations and no unconnected nets at JLCPCB 4-layer rules. The verification report has 24 measured checks with no failures, the firmware builds to a flashable UF2, and the fab files are ready to order.

RP2040 · SKiDL · KiCad · Pico SDK (C) · Freerouting · INA219 · I²C

GitHub

Experience

  1. Apr 2026 to Present

    ECU Design & Validation Intern · Bosch

    Plymouth, MI

    • Perform hardware bring-up, system-level validation, and electrical debug of chassis-control ECUs with oscilloscopes, waveform generators, and DMMs across 20+ bench and in-vehicle test scenarios.
    • Analyze signal integrity, impedance behavior, and communication reliability across embedded interfaces and ECU subsystems to support hardware validation and fault isolation.
    • Debug hardware and communication interfaces (I²C, SPI, UART) through targeted waveform analysis and systematic, subsystem-level fault isolation.

  2. Apr 2026 to Present

    Systems Engineering Lead · NASA L'SPACE Program

    Remote

    • Lead system-level architecture and trade studies for a simulated NASA mission, defining 15+ subsystem requirements across power, communications, and payload systems.
    • Coordinate cross-functional design reviews within a 10+ member team, driving iterative refinement of mission performance under realistic aerospace constraints.

  3. Sep 2025 to May 2026

    Research Assistant · Human-Automation Technology Lab, MSU

    East Lansing, MI

    • Developed multimodal (audio + inertial) pipelines for real-time speaker and emotion recognition on embedded targets.
    • Reduced MFCC, RMS, and ZCR feature computation by roughly half for embedded deployment. This work fed into the MWSCAS 2026 paper below.

  4. Sep 2019 to Jun 2025

    Head Manager, Audio & Visual Systems · Korean Presbyterian Church of Metro Detroit

    Detroit, MI

    • Designed and maintained multi-channel audio systems for 500+ person events while leading an 8-member team.

  5. Education

    University of Michigan

    B.S. Electrical & Electronics Engineering, Minor in Computer Science

    Ann Arbor, MI · Expected 2028

    Michigan State University, Honors College

    B.S. Electrical Engineering (transferred)

    East Lansing, MI · GPA 3.7 · 2025 to 2026

Research

AcceptedIEEE MWSCAS 2026

Evaluating Edge Speaker Verification ML Pipelines: A Multi-Variable Optimization Framework

Nitish Maindoliya, Chenxin Zhang, Jaden Rhee, and Andrew J. Mason

We profiled 225 combinations of audio features and classifiers for real-time speaker verification on microcontrollers with 512 KB of memory. Classic DSP features feeding an RBF-kernel SVM landed on the best tradeoff of accuracy, latency, and memory, where deep learning embeddings were too heavy to fit.

Read the paper (PDF)

Get in touch

Email is the fastest way to reach me.

jadenrhee619@gmail.comRésumé (PDF)
GitHubLinkedIn